1. Field of the Invention
The present invention relates to a voltage regulator with very quick response.
2. Description of the Related Art
As is known, the response time of a voltage regulator depends upon various factors, amongst which are the dimensions of the capacitances connected to the node to be regulated and the maximum current delivered by the regulator. Clearly, the stability of the voltage on the node to be regulated is affected by the response time of the regulator. Following upon a disturbance, in fact, the charge accumulated on the capacitances connected to the node to be regulated is modified, and the voltage returns to the nominal value only when the regulator has restored that charge. In practice, the voltage on the node to be regulated is never rigorously constant, but has oscillations around the nominal value (i.e., ripple). The regulator has to reduce the amplitude of this ripple and attenuate it as fast as possible.
Furthermore, some regulated circuits have an impulsive type behavior, which is critical for the regulator. In particular, when some of the load capacitances can be selectively connected to the regulator through switches, closing of these switches causes a sudden absorption of very high currents, as said in an impulsive way. This situation arises, for example, in case of voltage regulators for reading/writing memory arrays, especially ones of a non-volatile type. It is in fact known that a memory array comprises a plurality of cells organized in rows and columns; cells belonging to a same row have gate terminals connected to a same wordline, while cells belonging to a same column have drain terminals connected to a same bitline. High capacitances are hence associated with each wordline and bitline. In particular, when a cell is selected for reading/writing, the corresponding wordline is connected to a voltage regulator through one or more switches, and the associated capacitance absorbs an impulsive current.
Normally, to reduce the ripple of the regulated voltage a buffer capacitor is used, which is connected directly to the output of the regulator, upstream of the switches. The buffer capacitor may be an independent component arranged at the output of the regulator or, alternatively, a part of the capacitive load stably connected to the output of the regulator. Upon closing of the switches, the charge stored on the buffer capacitor is shared with the load capacitances, and thus the variation of the regulated voltage depends upon the ratio between the capacitance of the buffer capacitor and the total capacitance connected in parallel to the output of the regulator, i.e., the sum of the capacitance of the buffer capacitor and the capacitance of the load capacitor: in particular, the greater the capacitance of the buffer capacitor, the smaller the ripple of the regulated voltage. On the other hand, the time employed by the regulator for restoring the charge on the buffer capacitor increases as its capacitance increases. In practice, then, the need to reduce the ripple is in contrast with the requirement of quick response, and it is not possible to reach optimal compromises.
In order to overcome this drawback, voltage regulators having a boost stage have been proposed. For greater clarity, see FIG. 1, wherein a voltage regulator 1 is illustrated, which comprises a differential amplifier 2, a control unit 4, and a boost circuit 5. FIG. 1 further illustrates a a buffer capacitance CT, here represented by a buffer capacitor 3 statically connected to an output terminal 1a of the regulator 1, and a load circuit 6 that includes a switched capacitance CL, here illustrated schematically by means of a load capacitor 7, which can be selectively connected to the output terminal 1a through a switch 8. in practice, there is therefore a fixed capacitive component and a variable capacitive component, i.e., the buffer capacitance CT and, respectively, the switched capacitance CL. The fixed component is constantly connected to the output terminal 1a of the regulator 1, while the variable component is set in parallel to the fixed component only following upon closing of the switch 8.
The differential amplifier 2 has an inverting input connected to a reference-voltage source 10, which supplies a constant band-gap voltage VBG, an inverting input connected to an intermediate node 11 of a resistance divider 12, and an output, which is connected to the output terminal 1a and which supplies a regulated voltage VR. Furthermore, the resistance divider 12 is connected between the output terminal 1a and ground in parallel to the buffer capacitor 3.
The boost circuit 5 comprises a drive stage 14 and a boost capacitor 15, which has a boost capacitance CB. The drive stage 14, here a CMOS inverter comprising an NMOS transistor 17 and a PMOS transistor 18, has an input 14a receiving a boost signal B of a logic type generated by the control unit 4, and an output connected to a first terminal 15a of the boost capacitor 15. In addition, the drive stage 14 has a first supply terminal, connected to a voltage-boosted line 16, which supplies a boosted voltage VA higher than the regulated voltage VR, and a second supply terminal connected to ground. In particular, the NMOS transistor 17 and PMOS transistor 18 have gate terminals connected to the input 14a and drain terminals connected to the output and, thus, to the first terminal 15a of the boost capacitor 15. A second terminal of the boost capacitor 15 is connected to the output terminal 1a of the regulator 1.
The boost signal B is synchronized with the switch 8. In particular, when the switch 8 is open, the boost signal B is high; Consequently, the PMOS transistor 18 is off, and the NMOS transistor 17 is on and grounds the first terminal 15a of the boost capacitor 15, which accumulates a boost charge QB. When, instead, the switch 8 is closed, the boost signal B is low; in this case, the NMOS transistor 17 is off, while the PMOS transistor 18 connects the first terminal 15a of the boost capacitor 15 to the voltage-boosted line 16. The boost charge QB, previously accumulated on the boost capacitor 15, is then injected into the output terminal 1a and absorbed by the load circuit 6. It is possible to size the boost capacitor 15 and the value of the boosted voltage VA so that the boost charge QB injected into the output terminal 1a (QB=CBVA) is substantially equal to the charge absorbed by the load circuit 6. In this way, the ripple of the regulated voltage VR is considerably reduced.
However, the known regulators have some limitations. In fact, after the boost capacitor 15 has been discharged, it must again absorb the boost charge QB, when its first terminal 15a is grounded. Thus, a condition arises which is altogether similar to the sudden absorption of current by the load circuit 6, and hence the regulated voltage VR is subject to ripple. To prevent this ripple, the drive circuit 14 that takes the first terminal 15a of the boost capacitor 15 from the boosted voltage VA to ground is usually switched gradually. It is clear that, in this way, the transition is also slower. Consequently, the regulator 1 is not suited for being used at high frequencies, as, instead, is required increasingly more frequently in numerous applications.